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MRF89XA
3.7
Sync Word Recognition
3.7.2
PACKET HANDLER
Sync word recognition (also called as pattern
recognition) is activated by setting the SYNCREN bit
(SYNCREG<5>). The bit synchronizer must be
The packet handler is the block used in Packet mode.
Its functionality is described in Section 3.11, Packet
Mode .
activated. The block behaves like a shift register; it
continuously compares the incoming data with its
3.7.3
CONTROL
internally programmed Sync word and asserts the Sync
IRQ source on each occasion that a match is detected.
This is illustrated in Figure 3-15 .
During the comparison of the demodulated data, the
first bit received is compared with bit 7 (MSb) of the
byte at address 22 and the last bit received is com-
The control block configures and controls the behavior
of the MRF89XA according to the settings programmed
in the configuration registers.
3.7.4 SYNC REGISTERS
The registers associated with SYNC are:
pared with bit 0 (LSb) of the last byte whose address is
determined by the length of the Sync word. When the
programmed Sync word is detected the user can
assume that this incoming packet is for the node and
can be processed accordingly.
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GCONREG ( Register 2-1 )
DMODREG ( Register 2-2 )
FDEVREG ( Register 2-3 )
BRSREG ( Register 2-4 )
3.7.1
CONFIGURATION
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FLTHREG ( Register 2-5 )
FIFOCREG ( Register 2-6 )
Size: Sync word size can be set to 8, 16, 24 or 32 bits
through the SYNCWSZ<1:0> bits (SYNCREG<5:4>).
In Packet mode this field is also used for Sync word
generation in TX mode.
Error Tolerance: The number of errors tolerated in the
Sync word recognition can be set to 0, 1, 2 or 3 through
the SYNCTEN<1:0> bits (SYNCREG<2:1>).
Value: The Sync word value is configured in the Sync
Word Parameters in the related Configuration Regis-
ters. In Packet mode this field is also used for Sync
word generation in TX mode.
FIGURE 3-15:
SYNC WORD RECOGNITION
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FTXRXIREG ( Register 2-14 )
FTPRIREG ( Register 2-15 )
RSTHIREG ( Register 2-16 )
FILCREG ( Register 2-17 )
PFCREG ( Register 2-18 )
SYNCREG ( Register 2-19 )
RSTSREG ( Register 2-21 )
OOKCREG ( Register 2-22 )
SYNCV31REG ( Register 2-23 )
SYNCV23REG ( Register 2-24 )
RX DATA
(NRZ)
Bit N-x =
SSYNCVAL<x>
Bit N-1 =
SYNCVAL<0>
Bit N =
SYNCVAL<0>
DCLK
SYNC
DS70622C-page 72
Preliminary
? 2010–2011 Microchip Technology Inc.
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